specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. the products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appli ances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliab ility and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the intended use. if there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. 80112hkpc 20120531-s00006 no.a2081-1/29 ver1.0.0 LC786961W overview the LC786961W integrates arm7tdmi-s?, cd servo control, cd signal processing, compressed audio decode processing, audio signal processing, usb host processing, sd memory card host processing and a flash memory to store the program for arm7tdmi-s? and various data in a package. furthermore, various kinds of interface functions such as sio, uart etc. reduce the external main controller?s processing load and make high performance and much functional cd player system, using with less components. features ? rf signal processing for cd-da/r/rw, servo control, efm signal processing, and anti-shock processing ? mp3*, wma*, aac* decoder processing ? sampling rate convertor, high frequency compensation filter and other various audio signal processing ? usb host function (full speed as 12mbps), sd memory card host function ? arm7tdmi-s? as internal cpu core, flash me mory for program and various data storage ? operating voltage: 3.3v typical ? operating temperature: -40 c to +85 c ? packages: sqfp144 (20 20) ordering number : ena2081 cmos lsi compact disc player ic is a registered trademark of arm limited. * mp3(mpeg layer-3 audio coding) mpeg layer-3 audio coding technology li censed from fraunhofer iis and thomson. supply of this product does not convey license under the releva nt intellectual property of thomson and/or fraunhofer gesellscha ft nor imply any right to use this product in any finished end user or ready- to-use final product. an independent license for such use is r equired. for details, please visit http://mp3licensing.com/ . * windows media audio windows media tm is a trademark and a registered trademark in the united states and other countries of united states microsoft corporation. * aac advanced audio coding * this product incorporates t echnology licensed from silic on storage technology inc.
LC786961W no.a2081-2/29 detail of functions [ cd dsp functions ] ? playback mode: clv playback/jitter free playback (vcec) ? playback speed: normal speed, double speed , quadruple speed ? rf system:agc, cd-r and cd-r/w playback support, peak hold, bottom hold ? error system: te signal generation, fe signal generation ? detection: track count signal, jitter, defect (black, mirror) ? laser power controller (apc) ? dc offset voltage cancellation ? all servo systems as tracking, focus, sled and spindle are implemented with digital processing. ? automatic adjustment functions: focus gain, focus bias, focus offset, tracking gain, tracking offs et and tracking balance ? shock detection / interruption detection ? efm signal synchronization detection, protection and interpolation ? error detection, correction (c1=double, c2=quadruple/double) ? jitter margin 19 frames ? buffers cd-text data to the desired area of sdram ? starts buffering desired id3/id4 of cd-text data. ? anti-shock processing using with sdram maximum about 10 seconds with 16m bit sdram and about 40 seconds with 64m bit sdram ? cd-rom decoding (mode1, mode2 ) ? outputs cd-rom decoded data [ compressed audio decode functions ] ? mp3 decode (iso/iec 11172-3, iso/iec 13818-3) sampling rate support: mpeg1-layer1/2/3 (32khz, 44.1khz, 48khz) mpeg2-layer1/2/3 (16khz, 22.05khz, 24khz) mpeg2.5-layer3 ( 8khz, 11.025khz, 12khz) bit rate support: all bit rate (variable bit rate support) mpeg header read support ? wma decode (version 9 standard) sampling rate support: 8khz, 11.025khz, 16khz, 22.05khz, 32khz, 44.1khz, 48khz bit rate support: 5kbps to 384kbps (variable bit rate support) ? aac decode (iso/iec 14496-3, iso/iec 13818-7) profile: mpeg4-aac-lowcomplexity sampling rate support: 8khz, 11.025khz, 12khz, 16khz, 22.05khz, 24khz, 32khz, 44.1khz, 48khz bit rate support: monaural 8kbps to 160kbps (variable bit rate support) stereo 16kbps to 320kbps (variable bit rate support) ? decodes both the compressed data read from the di sc and input from outside through the interface pins
LC786961W no.a2081-3/29 [ audio processing functions ] ? sampling rate converter (src) for compressed audio data playback ? high frequency compensation filter for compressed audio data playback ? interpolation (cd-da only) ? mute function (-12db, - ) ? digital attenuator ? de-emphasis filter ? bilingual function ? bass / treble filter ? eight-fold over-sampling digital filter (24bit) ? one bit dac (tertiary ? noise shaper type) ? secondary lpf for audio output ? allows external audio data supply to the dig ital filter and d/a converter (uses four signals) ? various external audio data output format iis (48fs/64fs), msb first right justified (32fs/48fs/64fs), 16 bit data length [ external interface functions ] ? open host controller interface 1.0a ? universal serial bus specification 1.1 supports up to full speed (12mhz)for usb2.0 ? supports four kinds of transfer type (control/bulk/interrupt/isochronous) ? multimedia card specification v2.11 ? secure digital memory card physical layer specification v0.96 * individual contract is necessary to use sd memory card controller. for detail, please contact to us. [ internal microcontroller functions ] ? cd, usb, sd memory card playback control servo control, cd anti-shock playback cont rol, cd-rom/usb/sd file analysis, etc. ? communication format: sio ? gpio port 30ports maximum (shared with other functions. several pins are 5v tolerant.) ? external interrupt pins 4pins maximum (shared with other functions.) ? serial interface sio clock synchronized full duplex (3 lines) 2 channel uart full duplex 2 channel iic master function 1 channel ? flash memory program version up from the external media (c d-rom/usb)or main controller is available. ? watch dog timer notify to outside from the pin or reset internally. ? power management 2 kinds of sleep mode (1) only cpu core operates at slow clock and clocks for other blocks are stopping. (2) all clocks are stopping.
LC786961W no.a2081-4/29 [ others ] ? external sdram memory size : 16mbit or 64mbit data width : 16bit cas latency : 2 burst length : full used for cd-da anti-shock control, cd-rom decoding, usb data temporary storage, etc. ? 1.5v regulator for internal blocks
LC786961W no.a2081-5/29 specifications absolute maximum ratings at ta = 25 c, dv ss = av ss = lrv ss = xv ss 1 = xv ss 2 = vv ss 1 = vv ss 2 = 0v parameter symbol pin names conditions ratings unit maximum supply voltage v dd max dv dd , av dd , lrv dd , xv dd 1, xv dd 2, uv dd , vv dd 1, vv dd 2, vv dd 3 -0.3 to +3.95 v input voltage 1 v in 1 input pins other than v in 2 -0.3 to dv dd +0.3 v input voltage 2 v in 2 resb, sifck, sifdi, sifdo, sifce, busyb, gp03, gp04, gp05, gp06, gp07, gp10, gp11, gp12, gp14, gp15, gp16, gp26, gp27, jtrstb, jtck, jtdi, jtms -0.3 to +5.6 v output voltage v out -0.3 to dv dd +0.3 v allowable power dissipation pd max ta 85 c mounted reference pcb (*) 540 mw operating temperature topr -40 to +85 c storage temperature tstg -40 to +125 c (*)reference pcb: 114.3mm76.1mm1.6mm, glass epoxy resin allowable operating ranges at ta = -40 to +85 c, dv ss = av ss = lrv ss = xv ss 1 = xv ss 2 = vv ss 1 = vv ss 2 = 0v parameter symbol pin names conditions min typ max unit supply voltage v dd 1 dv dd , av dd , lrv dd , xv dd 1, xv dd 2, uv dd , vv dd 1, vv dd 2, vv dd 3 3.00 3.60 v v ih (1) resb, sifck, sifdi, sifdo, sifce, busyb, gp03, gp04, gp05, gp06, gp07, gp10, gp11, gp12, gp14, gp15, gp16, gp26, gp27, jtms, jtrstb, jtck, jtdi schmitt 2.00 5.50 v high-level input voltage v ih (2) gp13, gp17, gp20, gp21, gp22, gp23, gp24, gp25, gp60, gp61, gp62, gp63, gp64, gp65, sddat00 to sddat15, pmode0, pmode1 schmitt 2.00 v dd 1v v il (1) resb, sifck, sifdi, sifdo, sifce, busyb, gp03, gp04, gp05, gp06, gp07, gp10, gp11, gp12, gp14, gp15, gp16, gp26, gp27, jtms, jtrstb, jtck, jtdi schmitt 0 0.80 v low-level input voltage v il (2) gp13, gp17, gp20, gp21, gp22, gp23, gp24, gp25, gp60, gp61, gp62, gp63, gp64, gp65, sddat00 to sddat15, mode0, mode1, mode2 schmitt 0 0.80 v xin fx1 xout oscillator circuit 12.0 mhz x16in crystal oscillator frequency fx2 x16out oscillator circuit 16.9344 mhz
LC786961W no.a2081-6/29 electrical characteristics at ta = -40 to +85 c, v dd 1 = 3.0v to 3.6v, dv ss = av ss = lrv ss = xv ss 1 = xv ss 2 = vv ss 1 = vv ss 2 = 0v parameter symbol pin names conditions min typ max unit current drain i dd 1 dv dd , av dd , lrv dd , xv dd 1, xv dd 2, uv dd , vv dd 1, vv dd 2, vv dd 3 125 150 ma i ih (1) resb, sifck, sifdi, jtms, jtrstb, jtck, jtdi, pmode0, pmode1, sifdo, sifce, busyb, gp03, gp04, gp05, gp06, gp07, gp10, gp11, gp12, gp14, gp15, gp16, gp26, gp27 schmitt, v in = 5.50v built-in pull-down resistor off 10.00 a high-level input current i ih (2) gp13, gp17, gp20, gp21, gp22, gp23, gp24, gp25, gp60, gp61, gp62, gp63, gp64, gp65, sddat00 to sddat15 schmitt, v in = v dd 1 built-in pull-down resistor off 10.00 a low-level input current i il (1) resb, sifck, sifdi, sifdo, sifce, busyb, gp03, gp04, gp05, gp06, gp07, gp10, gp11, gp12, gp13, gp14, gp15, gp16, gp17, gp20, gp21, gp22, gp23, gp24, gp25, gp26, gp27, gp60, gp61, gp62, gp63, gp64, gp65, sddat00 to sddat15, jtms, jtrstb, jtck, jtdi, mode0, mode1, mode2 schmitt, v in = 0v -10.00 a v oh (1) gp04, gp05, gp06, gp07, gp12, gp13, gp14, gp15, gp16, gp17, gp20, gp21, gp22, gp23, gp24, gp25, gp26, gp27, gp60, gp61, gp62, gp63, gp64, gp65, sdba, sddat00 to sddat15, sdadrs00 to sdadrs12, sdcsb, sdrasb, sdcasb, sdweb, sdcke, sddqm cmos, i oh = -2ma v dd 1-0.6 v high-level output voltage v oh (2) sifdi, sifdo, sifce, busyb, gp03, gp10, gp11, sdclk, jtdo, jtrtck cmos, i oh = -4ma v dd 1-0.6 v v ol (1) gp04, gp05, gp06, gp07, gp12, gp13, gp14, gp15, gp16, gp17, gp20, gp21, gp22, gp23, gp24, gp25, gp26, gp27, gp60, gp61, gp62, gp63, gp64, gp65, sdba, sddat00 to sddat15, sdadrs00 to sdadrs12, sdcsb, sdrasb, sdcasb, sdweb, sdcke, sddqm cmos, i ol = 2ma 0.40 v low-level output voltage v ol (2) sifdi, sifdo, sifce, busyb, gp03, gp10, gp11, sdclk, jtdo, jtrtck cmos, i ol = 4ma 0.40 v ioff(1) pdout0, pdout1, afilt hi-z out -10.00 10.00 a output off-leakage current ioff(2) sifdo hi-z out -10.00 10.00 a continued to the next page.
LC786961W no.a2081-7/29 continued from the previous page. parameter symbol pin names conditions min typ max unit built-in pull down resistor rp d sifdo, sifce, busyb, gp03, gp04, gp05, gp06, gp07, gp10, gp11, gp12, gp13, gp14, gp15, gp16, gp17, gp20, gp21, gp22, gp23, gp24, gp25, gp26, gp27, gp60, gp61, gp62, gp63, gp64, gp65, sddat00 to sddat15 50 100 200 k ipdoh pdout1, pdout0 42.50 50.00 57.50 a ipdol pdout1, pdout0 pckist = 100k current value setting: 1x -57.50 -50.00 -42.50 a iafilh afilt 15.0 a charge pump output current iafill afilt 15.0 a ? put a internal pull down resistor or external pull down resi stor or external pull up resistor to the sifdo pin if its output condition is set to 3-state mode. package dimensions unit : mm (typ) 3214a sanyo : sqfp144 (20x20) 20.0 22.0 20.0 22.0 0.145 0.2 0.5 (1.25) 0.5 136 37 72 73 108 109 144 (1.4) 1.6max 0.1
LC786961W no.a2081-8/29 pin assignment lc786961 vv dd 3 afilt vv ss 2 vv dd 2 uv dd udp udm xv ss 1 xout xin xv dd 1 gp07 gp06 gp05 gp04 gp03 busyb sifce sifdo sifdi sifck resb dv ss dv dd mode1 mode0 sddat00 sddat01 sddat02 sddat03 sddat04 sddat05 sddat06 sddat07 sdweb sdcasb 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 slco lrv ss rcho lrref lcho lrv dd xv dd 2 x16in x16out xv ss 2 gp65 gp64 gp63 gp62 gp61 gp60 gp17 gp16 gp15 gp14 dv dd 15 dv ss dv dd gp25 gp24 gp23 gp22 gp21 gp20 jtrtck jtdo jtms jtdi jtck jtrstb mode2 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 efmin rfout lpf phlpf ain cin bin din slciset rfmon vref jittc ein fin te tein ldd lds av ss av dd yad01 yad02 fdo tdo sldo spdo vv dd 1 pdout1 pdout0 pcncnt pckist vv ss 1 pmode0 pmode1 gp26 gp27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 gp10 gp11 gp12 gp13 sddat15 sddat14 sddat13 sddat12 dv dd dv ss sddat11 sddat10 sddat09 sddat08 sddqm sdclk sdcke sdadrs11 sdadrs09 dv dd dv ss dv dd 15 sdadrs08 sdadrs07 sdadrs06 sdadrs05 sdadrs04 sdadrs03 sdadrs02 sdadrs01 sdadrs00 sdadrs10 sdba sdadrs12 sdcsb sdrasb 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 top view
LC786961W no.a2081-9/29 pin description pin no. pin name i/o state when "reset" function 1 efmin ai input rf signal input 2 rfout ao undefined rf signal output 3 lpf ao undefined rf signal dc level detecti on low-pass filter capacitor connection 4 phlpf ao undefined defect detection low-pass filter capacitor connection 5 ain ai input a signal input 6 cin ai input c signal input 7 bin ai input b signal input 8 din ai input d signal input 9 slciset ai input slco output current setting resistor connection 10 rfmon ao undefined ic internal analog signal monitor 1 11 vref ao av dd /2 vref voltage output 12 jittc ao undefined jitter de tection capacitor connection 13 ein ai input e signal input 14 fin ai input f signal input 15 te ao undefined te signal output 16 tein ai input te signal input used for tes signal generation 17 ldd ao undefined laser power control signal output 18 lds ai input laser power detection signal input 19 av ss - - analog system ground. this pin must be connected to the 0v level. 20 av dd - - analog system power supply 21 yado1 ai/ao input ad input 1/fe signal monitor output 22 yado2 ai/ao input ad input 2/ic internal analog signal monitor 2 23 fdo ao av dd /2 focus control signal output 24 tdo ao av dd /2 tracking control signal output 25 sldo ao av dd /2 sled control signal output 26 spdo ao av dd /2 spindle control signal output 27 vv dd 1 - - efmpll power supply 28 pdout1 ao undefined efmpll charge pump output 1 29 pdout0 ao undefined efmpll charge pump output 0 30 pcncnt ai input efmpll charge pump control voltage input 31 pckist ai input efmpll charge pump current setting resistor connection pin 32 vv ss 1 - - efmpll ground. this pin must be connected to the 0v level. 33 pmode0 i input must be connected to the dv dd . 34 pmode1 i input must be connected to the dv dd . 35 gp26 i/o input (l) general purpose i/o port with pull down resistor 36 gp27 i/o input (l) general purpose i/o port with pull down resistor 37 gp10 i/o input (l) general purpose i/o port with pull down resistor uart1 data transmit 38 gp11 i/o input (l) general purpose i/o port with pull down resistor uart1 data receive 39 gp12 i/o input (l) general purpose i/o port with pull down resistor clock control input 1 40 gp13 i/o input (l) general purpose i/o port with pull down resistor clock control input 2 watch dog timer state monitor output sdram lower byte data mask control output sdram-dqml (ldqm) pin should be connected for 64mbit-sdram (only when ?byte access? is enabled.) 41 sddat15 i/o input (l) sdram data input/output 15 (pull down resistor) 42 sddat14 i/o input (l) sdram data input/output 14 (pull down resistor) 43 sddat13 i/o input (l) sdram data input/output 13 (pull down resistor) 44 sddat12 i/o input (l) sdram data input/output 12 (pull down resistor) 45 dv dd - - digital system power supply 46 dv ss - - digital system ground. this pin must be connected to the 0v level. continued to the next page.
LC786961W no.a2081-10/29 continued from the previous page. pin no. pin name i/o state when "reset" function 47 sddat11 i/o input (l) sdram data input/output 11 (pull down resistor) 48 sddat10 i/o input (l) sdram data input/output 10 (pull down resistor) 49 sddat09 i/o input (l) sdram data input/output 9 (pull down resistor) 50 sddat08 i/o input (l) sdram data input/output 8 (pull down resistor) 51 sddqm o low sdram data mask control output sdram-dqmh(udqm) pin should be connected both for 16m and 64mbit-sdram. 52 sdclk o low sdram clock output 53 sdcke o low sdram clock enable output 54 sdadrs11 o low sdram address output 11 no use (nc) for 16mbit-sdram sdram-adrs11 pin connection for 64mbit-sdram 55 sdadrs09 o low sdram address output 9 56 dv dd - - digital system power supply 57 dv ss - - digital system ground. this pin must be connected to the 0v level. 58 dv dd 15 ao high capacitor connection pin for internal regulator 59 sdadrs08 o low sdram address output 8 60 sdadrs07 o low sdram address output 7 61 sdadrs06 o low sdram address output 6 62 sdadrs05 o low sdram address output 5 63 sdadrs04 o low sdram address output 4 64 sdadrs03 o low sdram address output 3 65 sdadrs02 o low sdram address output 2 66 sdadrs01 o low sdram address output 1 67 sdadrs00 o low sdram address output 0 68 sdadrs10 o low sdram address output 10 69 sdba o low sdram bank select address output sdram-bank pin connection for 16mbit-sdram sdram-bank1 pin connection for 64mbit-sdram 70 sdadrs12 o low sdram address output 12 sdram-dqml (ldqm) pin connection for 16mbit-sdram. sdram-bank0 pin connection for 64mbit-sdram 71 sdcsb o low sdram chip select output 72 sdrasb o low sdram row address strobe output 73 sdcasb o low sdram column address strobe output 74 sdweb o low sdram write enable output 75 sddat07 i/o input (l) sdram data input/output 7 (pull down resistor) 76 sddat06 i/o input (l) sdram data input/output 6 (pull down resistor) 77 sddat05 i/o input (l) sdram data input/output 5 (pull down resistor) 78 sddat04 i/o input (l) sdram data input/output 4 (pull down resistor) 79 sddat03 i/o input (l) sdram data input/output 3 (pull down resistor) 80 sddat02 i/o input (l) sdram data input/output 2 (pull down resistor) 81 sddat01 i/o input (l) sdram data input/output 1 (pull down resistor) 82 sddat00 i/o input (l) sdram data input/output 0 (pull down resistor) 83 mode0 i input lsi mode set pin 0 this pin must be connected to the 0v level. 84 mode1 i input lsi mode set pin 1 this pin must be connected to the 0v level. 85 dv dd - - digital system power supply 86 dv ss - - digital system ground. this pin must be connected to the 0v level. 87 resb i - ic reset input ("l"-active) this pin must be set low once after power is first applied. 88 sifck i input host-i/f data transmit clock input for serial communication 1 89 sifdi i/o input host-i/f data input for serial communication 1 continued to the next page.
LC786961W no.a2081-11/29 continued from the previous page. pin no. pin name i/o state when "reset" function 90 sifdo i/o input host-i/f data output for serial communication 1 (cmos or 3-state output) 91 sifce i/o input host -i/f enable signal input for serial communication 1 ("h"-active) 92 busyb i/o input (l) host -i/f system busy signal output ("l"-active) 93 gp03 i/o input (l) general purpose i/o port with pull down resistor usb device detection flag output 94 gp04 i/o input (l) general purpose i/o port with pull down resistor iic (master) clock output 95 gp05 i/o input (l) general purpose i/o port with pull down resistor iic (master) data input/output 96 gp06 i/o input (l) general purpose i/o port with pull down resistor 97 gp07 i/o input (l) general purpose i/o port with pull down resistor 98 xv dd 1 - - oscillator power supply 99 xin i oscillation 12mhz oscillator connection 100 xout o oscillation 12mhz oscillator connection 101 xv ss 1 - - oscillator ground. this pin must be connected to the 0v level. 102 udm i/o - usb data input/output d- signal connection 103 udp i/o - usb data input/output d+ signal connection 104 uv dd - - usb power supply 105 vv dd 2 - - system pll power supply 106 vv ss 2 - - system pll ground. this pin must be connected to the 0v level. 107 afilt ao undefined audio pll charge pump output 108 vv dd 3 - - audio pll power supply 109 mode2 i input lsi mode set pin 2 this pin must be connected to the 0v level. 110 jtrstb i input jtag reset input (connect to pll-down resister or 0v level in normal mode.) 111 jtck i input jtag clock input (connect to pll-down resister or 0v level in normal mode.) 112 jtdi i input jtag data input (connect to pll-down resister or 0v level in normal mode.) 113 jtms i input jtag mode input (connect to pll-up resister or dv dd level in normal mode.) 114 jtdo o low jtag data output (leave open in normal mode.) 115 jtrtck o low jtag return clock output (leave open in normal mode.) 116 gp20 i/o input (l) general purpose i/o port with pull down resistor data 1 input/output for sd memory card 117 gp21 i/o input (l) general purpose i/o port with pull down resistor data 0 input/output for sd memory card 118 gp22 i/o input (l) general purpose i/o port with pull down resistor clock output for sd memory card 119 gp23 i/o input (l) general purpose i/o port with pull down resistor command input/output for sd memory card 120 gp24 i/o input (l) general purpose i/o port with pull down resistor data 3 input/output for sd memory card 121 gp25 i/o input (l) general purpose i/o port with pull down resistor data 2 input/output for sd memory card 122 dv dd - - digital system power supply 123 dv ss - - digital system ground. this pin must be connected to the 0v level. 124 dv dd 15 ao high capacitor connection pin for internal regulator 125 gp14 i/o input (l) general purpose i/o port with pull down resistor 126 gp15 i/o input (l) general purpose i/o port with pull down resistor 127 gp16 i/o input (l) general purpose i/o port with pull down resistor 128 gp17 i/o input (l) general purpose i/o port with pull down resistor 129 gp60 i/o input (l) general purpose i/o port with pull down resistor 130 gp61 i/o input (l) general purpose i/o port with pull down resistor continued to the next page.
LC786961W no.a2081-12/29 continued from the previous page. pin no. pin name i/o state when "reset" function 131 gp62 i/o input (l) general purpose i/o port with pull down resistor 132 gp63 i/o input (l) general purpose i/o port with pull down resistor 133 gp64 i/o input (l) general purpose i/o port with pull down resistor 134 gp65 i/o input (l) general purpose i/o port with pull down resistor 135 xv ss 2 - - oscillator ground. this pin must be connected to the 0v level. 136 x16out o oscillation 16.9344mhz oscillator connection 137 x16in i oscillation 16.9344mhz oscillator connection 138 xv dd 2 - - oscillator power supply 139 lrv dd - - audio lpf power supply 140 lcho ao lrv dd /2 audio lch data output 141 lrref ao lrv dd /2 reference voltage for audio lpf 142 rcho ao lrv dd /2 audio rch data output 143 lrv ss - - audio lpf ground. this pin must be connected to the 0v level. 144 slco ao undefined slice level control output (1) for unused pins: ? the unused input pins must be connected to the gnd (0v) level if there is no individual note in the above table. ? the unused output pins must be left open (no connection) if there is no individual note in the above table. ? the unused input/output pins must be connected to the gnd (0v) or power supply pin for i/o block with internal pull down resistor off or be left open with internal pull down resistor on when input pin mode or must be left open (no connection) when output pin mode if there is no individual note in the above table. when you connect an i/o pin which is an input pin withou t internal pull-down resistor at reset mode to the gnd or power supply level, we recommend you to use pull-down resistor or pull-up resistor individually as fail-safe. (2) for power supply pins: ? same voltage level must be supplied to dv dd , av dd , xv dd 1, xv dd 2, vv dd 1, vv dd 2, vv dd 3, uv dd and lrv dd power supply pins. (refer to?allowable operating ranges?.) (3) for ?reset? condition: ? this lsi is not reset only by making the resb pin ?low?. refer to ?power on and reset contro l? for detail of ?reset? condition.
LC786961W no.a2081-13/29 block diagram external sdram data trans controller mp3/wma/aac decoder audio control deemphasis/ mute/att external-in/out 8fs digital filter 1bit dac analog lpf interrupt uart iic sio gpio cdrom decoder cdtext decoder cdda anti shock bufram i/f audio data-i/f src & hfc-filter usb host controller work ram boot rom watchdog timer cd pll usb-i/f flash memory host-i/f (sio/iic) x?tal-2 (16.9344mhz) x?tal-1 (12mhz) apll syspll regulator cd rf signal processor ad/da sd memory card controller cd servo controller arm7 core cache cd efm/ecc decoder 1.5v 3.3v
LC786961W no.a2081-14/29 power on and reset control ? attention when power on the resb pin must be set to ?low? level to initialize the operating state of internal flash memory. if the power is on during the resb pin is ?high? level, th is lsi may operate incorrectly because the internal flash memory is not initialized. in this case, this lsi is not initialized even if a low level supplied to resb pin. therefore, the resb pin must be set to ?low? level when power is first supplied. you may input the voltage of 3.6v or less to each input pin when the power supply is off. however, it is necessary to supply a regulated voltage to the power supply pin before hand when more than 3.6v voltage is input to the 5v tolerant input pins. power on/power down/reset timing vbot tpwd tresw1 tresw2 3.3v power v dd 1 3.3v power v dd 1 resb 0v power on stage during normal operation (oscillation clock is valid) parameter symbol min typ max unit power down time tpwd 10 ms power down voltage vbot 0 0.2 v reset time (power on) tresw1 20 ms reset time (normal) (*1) tresw2 1 ms *1: the specification of tresw2 above is the time defined while steady the x16 clock and having oscillated. when the x16 clock has been stopped by the command etc. , the specification of tresw2 could be larger than the value shown above, because it takes time that the x16 oscillator becomes stable.
LC786961W no.a2081-15/29 host interface the data transmission between this lsi and host controller is performed with spi type synchronous sio protocol. the transmission procedure is as follows. ? refer to the internal software speci fication of this lsi about m5 to m0 code in mode code transmission. when the input data of m5 to m0 coincide to the data in the internal register, the sifdo pin becomes to ?low? level (ack) then the transmission is enabled. when not coincide, the sifdo pin keeps ?high? level (nack) then the transmission is not enabled. ? the seventh data in mode code transmission shows whether the following procedure is the command transmission or the data reception. when the seventh data is ?low ?, the following procedure is command transmission. when the seventh data is ?high?, the following procedure is data reception. ? attention because the specifications of transmission timings are different depending on the internal cpu?s operating speed modes (low speed or normal speed). refer to the table in next page. communication interface format between host controller sifce mode (send) command 1 command 2 command n mode (receive) data 1 data 2 data n sifck sifdi sifdo busyb ack ack transmission/reception format between host controller (1) host: command transmission (2) host: data reception sifce 1 8 m5 m2 m4 m3 mode code byte 1st-data byte last-data byte nack ack m0 wr m1 d7 d2 d6 d5 d0 d1 2345678123 67 1 8 m5 m2 m4 m3 mode code byte 1st-data byte last-data byte nack ack m0 rd m1 d7 d2 d6 d5 d0 d1 2345678123 67 sifck sifdi sifdo busyb sifce sifck sifdi sifdo busyb
LC786961W no.a2081-16/29 communication timing specification between host controller sifce (input) sifck (input) sifdi (input) sifdo (output) busyb (output) tcdon tcdoh tcbst tcras tcdof tce tchd tckl tcwsu tcwhd tckh tcsu 1/fclk parameter symbol pin names min typ max unit sifck clock frequency fclk sifck 3.3 0.725 mhz sifck clock "h" level width tckh sifck 150 690 ns sifck clock "l" level width tckl sifck 150 690 ns transfer start enable time tce busyb, sifce 0 0 ns setup time for transfer start tcsu sifce, sifck 100 200 ns hold time for transfer end tchd sifce, sifck 100 200 ns setup time for sifdi tcwsu sifdi, sifck 75 75 ns hold time for sifdi tcwhd sifdi, sifck 75 200 ns output delay time for sifdo ?h? tcdoh sifdo, sifck 100 350 ns output delay time for sifdo tcras sifdo, sifck 100 350 ns turn on time for sifdo *1 tcdon sifdo, sifce 100 100 ns turn off time for sifdo *1 tcdof sifdo, sifce 150 150 ns busyb "l" level output delay time tcbst busyb 150 350 ns internal cpu operating speed m ode upper step : normal speed lower step : low speed * 1: the tcdon and tcdof specifications are for wh en the sifdo pin is set to the 3-state mode.
LC786961W no.a2081-17/29 usb specification at ta = -40 c to +85 c, v dd 1 = 3.0v to 3.6v, dv ss = av ss = lrv ss = xv ss 1 = xv ss 2 = vv ss 1 = vv ss 2 = 0v parameter symbol pin names conditions min typ max unit high-level input voltage v ih (usb) 2.0 low-level input voltage v il (usb) 0.8 v input leakage current ili output driver: off -10.0 10.0 a differential input sensitivity vdi |(udp) - (udm)| 0.2 v common mode voltage range vcm includes vdi range 0.8 2.5 v high-level output voltage v oh (usb) connect 15k 5% pull-down resistor to gnd (0v). 2.8 3.6 v low-level output voltage v ol (usb) connect 1.5k 5% pull-up resistor to v dd 1. 0 0.3 v crossover voltage vcr 1.3 2.0 v usb data rising time tur 4.0 20.0 usb data falling time tuf udm, udp cl = 50pf 4.0 20.0 ns example circuit for usb application lc786961 v dd 1 uv dd udp udm 5pf 15k 15 5pf 15k 15 * the value of resistors and capacitors in this circuit might be needed to be adjusted for each application.
LC786961W no.a2081-18/29 sd memory card interface sd memory card input/output timing specification tsdckl tsdcms tsdcds tsdcmh tsdcmo tsdcdh tsdcdo sdcclk (output) sdcmdio (inout) sdcdat[3:0] (inout) tsdckh 1/fsdckf * relationship between signal name and pin name sdcclk : gp22 sdcmdio : gp23 sdcdat [3] : gp24 sdcdat [2] : gp25 sdcdat [1] : gp20 sdcdat [0] : gp21 parameter symbol pin names min typ max unit sdcclk clock frequency fsdckf sdcclk 6.0 mhz sdcclk clock "h" level width tsdckh sdcclk 83.3 ns sdcclk clock "l" level width tsdckl sdcclk 83.3 ns setup time for command input tsdcms sdcmdio, sdcclk 30.0 ns hold time for command input tsdcmh sdcmdio, sdcclk 30.0 ns command output valid time tsdcmo sdcmdio, sdcclk 30.0 ns setup time for data input tsdcds sdcdat [3:0], sdcclk 30.0 ns hold time for data input tsdcdh sdcdat [3:0], sdcclk 30.0 ns data output valid time tsdcdo sdcdat [3:0], sdcclk 30.0 ns note: internal cpu (arm7) must be set to normal mode. never use the sd memory card interface at the internal cpu?s low speed mode.
LC786961W no.a2081-19/29 internal voltage regulator at ta = -40 c to +85 c, dv ss = av ss = lrv ss = xv ss 1 = xv ss 2 = vv ss 1 = vv ss 2 = 0v parameter symbol condition min typ max unit output voltage dv dd 15 v dd 1 = 3.0v to 3.6v 1.35 1.50 1.65 v load current iope v dd 1 = 3.3v 200 ma note : the spec. of ?load current? above is sum of the load current of two internal voltage regulator. example circuit for regulator lc786961 100 f c1 dv dd dv ss dv dd 15 a/d, d/a converter characteristics for servo at ta = -40 c to +85 c, v dd 1 = 3.3v, dv ss = av ss = lrv ss = xv ss 1 = xv ss 2 = vv ss 1 = vv ss 2 = 0v parameter symbol condition min typ max unit resolution res 8 bit maximum input/output range vaio1 4/5 v dd 1 v minimum input/output range vaio2 1/5 v dd 1 v 1-bit d/a converter characteristics at ta = 25 c, v dd 1 = 3.3v, dv ss = av ss = lrv ss = xv ss 1 = xv ss 2 = vv ss 1 = vv ss 2 = 0v parameter symbol pin names conditions min typ max unit output level level lcho, rcho with a 1khz, 0db data signal 0.63 vrms total harmonics distortion thd+n lcho, rcho with a 1khz, 0db data signal, using the 20khz low-pass filter (built-in ad725d) 0.008 0.012 % dynamic range dr lcho, rcho with a 1khz, -60db data signal, using the 20khz low-pass filter and a-filter (built-in ad725d) 92 96 db signal to noise ratio s/n lcho, rcho with a 1khz, 0db data signal, using the 20khz low-pass filter and a-filter (built-in ad725d) 95 98 db cross talk ct lcho, rcho with a 1khz, 0db data signal, using the 20khz low-pass filter (built-in ad725d) 82 85 db note : measured in normal speed playback mode in sanyo?s 1-bit d/a converter block reference circuit. 1-bit d/a converter output reference circuit lc786961 rcho :same circuit as for lcho 10 f 100 f 1000pf 100k 680 lpf analog outpu t left channel shibasoku co., ltd. ad725d lrv dd lcho lrref rcho lrv ss * same circuit need to be mounted both for two regulator pins. (no.58 and no.124) * the capacitor c1 must be greater than 50 f and low secure 50 f or more for low esr and the capacity value in the range of the operating temperature so that there is a possibility of the oscillation when the capacity value changes by the temperature change etc. (the recommended value is 100 f.)
LC786961W no.a2081-20/29 oscillator example circuit for oscillator lc786961 rd2 c2 c2 c1 c1 rd1 xv ss 1 xout xin xv dd 1 xv dd 2 x16in x16out xv ss 2 (1) xin/xout: 12.0000mhz ? for system main clock, usb control ? recommended oscillator nihon dempa kogyo co., ltd. type recommended value nx5032ga rd1 = 0 , c1 = 4pf nx8045gb rd1 = 0 , c1 = 4pf (2) x16in/x16out: 16.9344mhz ? for cd control, audio control ? recommended oscillator murata manufacturing co., ltd. type recommended value cstce16m9v53-r0 rd2 = 0 , c2 = open cstcw16m9x51008-r0 rd2 = 0 , c2 = open cstls16m9x53-b0 rd2 = 0 , c2 = open nihon dempa kogyo co., ltd. type recommended value at51-cd2 rd2 = 0 , c2 = 8pf < notes > ? because the characteristics of oscillator could be change d according to the circuit boar d, ask evaluation with the individual original circuit board to the oscillator maker. ? the accuracy of 12mhz oscillator (xin /xout) must be in 500ppm when this oscillator clock is used for usb host function. ? concerning about internal circuit for xin/xout and x16in/x16out, refer to the ?analog pin internal equivalent circuits? section.
LC786961W no.a2081-21/29 sdram interface (1) required specification for external sdram memory size :16mbit or 64mbit data width :16bit cas latency :2 burst length :full (2) interface pins to external sdram pin name function at 16mbit-sdram function at 64mbit-sdram signal name in cf. p24, p25 sddat15 to sddat00 data input/output (16bit) data input/output (16bit) ddat[15:0] ddat[15:0] sdadrs10 to sdadrs00 address output (11bit) address output (11bit) dadd[10:0] dadd[10:0] sdadrs11 not used address (a11) output - dadd[11] sdadrs12 dqml (ldqm) output lower byte data mask control address (a12) or bank0 output sddqml dadd[12] sdba bank output bank or bank1 output dadd[11] dadd[13] sddqm dqmh (udqm) output upper byte data mask control dqmh (udqm) output upper byte data mask control sddqmu sddqmu gp13 not used dqml (ldqm) output lower byte data mask control - sddqml sdcsb csb output csb output sdcsb sdcsb sdrasb rasb output rasb output sdrasb sdrasb sdcasb casb output casb output sdcasb sdcasb sdweb web output web output sdweb sdweb sdcke clock enable output clock enable output sdcke sdcke sdclk clock output clock output sdclk sdclk notes ? sdadrs11 and gp13 in 16mbit-sdram using mode should be treated as described below. sdadrs11 : open (no connect) gp13 : use as other function or open ? sddat00 to sddat15 pins can have internal pull down resistor optionally. those pull down resistors are set to on mode in initialization. when setting the sdram using mode, those pull down resistors will be set to off mode. ? some signals named in p22 to p23 use different pins according to the using sdram. the signal name in p22 to p23 for the actual pin is shown at the most right column in above table. upper step : signal name in 16mbit-sdram using mode lower step : signal name in 64mbit-sdram using mode
LC786961W no.a2081-22/29 (3) sdram access timing sdram read timing ts2 ts3 ts5 1/fs1 sdcsb sdclk sdcke sdrasb sdcasb sdweb dadd[13:0] row column row column all-pre sddqmu sddqml ddat[15:0] ts6 ts5 ts6 ts4 ts5 ts6 read-data cas-latency 2 ts10 ts11 ts7 ts8 ts9 ts7 ts7 sdram write timing ts2 ts3 ts5 1/fs1 sdcsb sdclk sdcke sdrasb sdcasb sdweb dadd[13:0] row column row column all-pre all-pre sddqmu sddqml ddat[15:0] ts6 ts5 ts6 ts6 ts5 write-data write-data data latch timing (sdram) ts12 ts13 ts8 ts9 ts7 ts5 ts6 ts7 ts7 ts7
LC786961W no.a2081-23/29 sdram refresh timing (auto refresh) ts14 ts15 ts5 1/fs1 sdcsb sdclk sdcke sdrasb sdcasb sdweb dadd[13:0] sddqmu sddqml ddat[15:0] ts6 ts5 ts6 ts7 ts7 symbol parameter min typ max unit fs1 sdram clock (sdclk) frequency 16.9344 mhz ts2 row (sdrasb) cycle time (1/fs1)5 ns ts3 row (sdrasb) active time (1/fs1)3 ns ts4 rasb-casb delay time (sdrasb-sdcasb) (1/fs1)2 ns ts5 command "l" level width (sdcsb, sdcke, sdr asb, sdcasb, sdweb) 40 ns ts6 command setup time (sdcsb, sdcke, sdrasb, sdc asb, sdweb, sddqmu, sddqml) 10 ns ts7 command hold time (sdcsb, sdcke, sdrasb, sdc asb, sdweb, sddqmu, sddqml) 10 ns ts8 address (dadd) setup time 10 ns ts9 address (dadd) hold time 10 ns ts10 sdram read data setup time (data read from sdram) 20 ns ts11 sdram read data hold time (data read from sdram) 0 ns ts12 sdram write data hold time before rising edge of sdclk (data write to sdram) 10 ns ts13 sdram write data hold time after rising edge of sdclk (data write to sdram) 10 ns ts14 row (sdrasb) pre-charge time (1/fs1)3 ns ts15 row (sdrasb) active time after refresh (1/fs1)5 ns notes ? setup time and hold time specifications in above table are measured from the rising edge of sdclk signal. ? all the specifications in above table are applied to read mode, write mode and refresh mode.
LC786961W no.a2081-24/29 analog pin internal equivalent circuits pin name (pin no.) equivalent circuit efmin (1) av dd av ss rfout (2) av dd av ss av dd av ss lpf (3) av dd av ss av dd av ss phlpf (4) av dd av ss ain (5) cin (6) bin (7) din (8) av dd av ss slciset (9) av dd av ss rfmon (10) av dd av ss av dd av ss continued to the next page.
LC786961W no.a2081-25/29 continued from the previous page. pin name (pin no.) equivalent circuit vref (11) av dd av dd av ss av ss jittc (12) av dd av ss ein (13) fin (14) av dd av ss te (15) av dd av ss av dd av ss tein (16) av dd av ss ldd (17) av dd av ss av dd av dd av ss lds (18) av dd av ss continued to the next page.
LC786961W no.a2081-26/29 continued from the previous page. pin name (pin no.) equivalent circuit yado1 (21) yado2 (22) av dd av ss fdo (23) tdo (24) sldo (25) spdo (26) av dd av ss av dd av ss pdout1 (28) vv dd 1 vv ss 1 vv dd 1 vv ss 1 pdout0 (29) vv dd 1 vv ss 1 vv dd 1 vv ss 1 pcncnt (30) vv dd 1 vv dd 1 vv ss 1 pckist (31) vv dd 1 vv ss 1 vv ss 1 xin (99) xout (100) xv dd 1 xin xout xv ss 1 xv dd 1 xv ss 1 continued to the next page.
LC786961W no.a2081-27/29 continued from the previous page. pin name (pin no.) equivalent circuit afilt (107) vv dd 3vv dd 3 vv ss 3 vv ss 3 x16out (136) x16in (137) xv dd 2 xin xout xv ss 2 xv dd 2 xv ss 2 lhco (140) rcho (142) lrv dd lrv ss lrv dd lrv ss lrref (141) lrv dd lrv ss lrv dd lrv ss slco (144) av dd av ss av dd av ss
LC786961W no.a2081-28/29 sample application circuit efmin slco to p i c k u p to d r i v e r rfout lpf phlpf a b c d e f ld md vref (reference voltage) ain cin bin din vv dd 3 afilt vv ss 2 vv dd 2 uv dd udp udm slciset lc786961 rfmon vref d+ d- from/to usb-device jittc ein fin te tein ldd lds av ss av dd yado1 yado2 fdo tdo sldo spdo vv dd 1 pdout1 pdout0 pcncnt pckist vv ss 1 gnd v dd 1 * this sample circuit is only for cd servo block, each pll block and usb block. the value of each component needs to be adjusted under the target conditions. the circuit for cd servo shown above could be changed depending on the cd mechanism used. concerning to the application circuit for regulator, au dio dac and oscillator, refe r to the page 19 and 20 respectively.
LC786961W no.a2081-29/29 ps sanyo semiconductor co.,ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. regarding monolithic semiconductors, if you should intend to use this ic continuously under high temperature, high current, high voltage, or drastic temperature change, even if it is used within the range of absolute maximum ratings or operating conditions, there is a possibility of decrease reliability. please contact us for a confirmation. sanyo semiconductor co.,ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. it is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equ ipment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. this catalog provides information as of august, 2012. specifications and information herein are subject to change without notice.
